The present invention relates to a semiconductor nonvolatile memory device and an information processing system employing such a memory device, to an effective technique for, for example, a batch erasable type EEPROM (electrically erasable and programmable read only memory), and also to a microcomputer system employing such an EEPROM.
As a semiconductor nonvolatile memory device, there are known an erasable programmable read-only memory (referred to as an AEPROM@) the stored information on which is erasable by utilizing ultraviolet radiation, and also an electrically erasable and programmable read-only memory (referred to as an “EEPROM”) the stored information of which is electrically erasable. An EPROM is suitable for a large-scale memory capacity because areas of memory cells for storing information are relatively small. However, to erase the information stored in EPROM, it is necessary to irradiate ultraviolet rays to the memory cells. To this end, a package having an ultraviolet irradiating window, which is relatively expensive, would be required in order to be able to employ such type of memory cells. Moreover, in order to be able to write or rewrite new information by a programmer, the EPROM must be removed, during write/rewrite operations thereof, from the system to which this EPROM has been actually packaged in, thereby resulting in a problem.
On the other hand, with respect to an EEPROM, the information stored therein is electrically erasable and writable, while the EEPROM remains packaged in a system. However, areas associated with memory cells of the EEPROM type are relatively large. For instance, a typical area of a memory cell in an EEPROM is 1.5 to 2 times, or as much as approximately 2.5 to 5 times, larger than that of an EPROM. Such an EEPROM is described, for example, in “Electronic Technology—June 1988”, pages 122-127, issued by K.K. Nikkan Kogyo Shimbun, in which a detailed description is made of a construction of an EEPROM cell of a floating-gate tunnel oxide (FLOTOX), a mechanism of injection of electrons into a floating gate and of release of electrons from the floating gate, and the like.
The EEPROM cell of the FLOTOX type is a memory cell having a two-layer construction provided with a floating gate for holding electrons in the lower layer of a control gate. This mechanism is designed so that a tunnel current called a Fowlor-Nordheim (F-N) is allowed to flow through a region (a tunnel region) of an extremely thin insulating film formed in a portion of an insulating film between the floating gate and a drain region to effect injection of electrons into the floating gate and release of electrons from the floating gate.
In the memory cell of EEPROM of the FLOTOX type, electrons held by the floating gate are released, for example, by applying a GND voltage (0 V) to the control gate and applying a high voltage of 15 V to 20 V to the drain electrode.
As a result of this relatively large size of the memory cells, in general, EEPROM is not suitable when emphasis is in having a large memory capacity.
Semiconductor nonvolatile memory devices that can be considered as being between or intermediate the EPROM and EEPROM, are so-called “electrically batch erasable type EEPROM” devices, or are flash EEPROM devices, which have very recently been developed. These devices are the semiconductor nonvolatile memory devices in which either all of the memory cells formed in a chip, or a certain memory cell group among the memory cells formed in the chip, are electrically erased. In accordance with the electrically batch erasable type of EEPROM, or the flash EEPROM, the size of memory cells thereof can be formed to be substantially the same as that of EPROM.
Such an electrically batch erasable type EEPROM is described in, for instance, IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1980, on pages 152 to 153; IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1987, on pages 76 to 77; and IEEE, J. SOLID-STATE CIRCUITS, vol. 23 (1988), pages 1157 to 1163.
In FIG. 16, there is represented a schematic sectional view of the electrically batch erasable EEPROM, which has been disclosed in the International Electron Device Meeting held in 1987. The memory cell shown in FIG. 16 is very similar to the memory cell of the normal EPROM. That is to say, this memory cell is constructed in accordance with an insulated gate type field-effect transistor (simply referred to as a “MOSFET” or “transistor”), however, having a double layer gate structure. In the structure of FIG. 16, reference numeral 8 indicates a P type silicon substrate; reference numeral 11 denotes a P type diffusion layer formed on the silicon substrate 8; reference numeral 10 represents an N type diffusion layer having a low concentration formed on the silicon substrate 8; and reference numeral 9 indicates an N type diffusion layer formed on each of the P type diffusion layer 11 and N type diffusion layer 10. Also, reference numeral 4 represents a floating gate formed on the P type silicon substrate 8 via a thin oxide film 7. Reference numeral 6 denotes a control gate formed on this floating gate 4 via the oxide film; reference numeral 3 indicates a drain electrode; and reference numeral 5 represents a source electrode. In other words, the memory cell shown in FIG. 16 is constructed like a MOSFET but having instead the N-channel type double gate structure. Thus, the information is stored in this transistor, and is held in this transistor in accordance with effecting a change of the threshold voltage thereof.
It should be noted that a transistor (referred to as a “storage transistor”) of a memory cell, for storing information, discussed herein is of an N-channel storage transistor unless stated otherwise in the following description.
The information writing operation with respect to the memory cell represented in FIG. 16 is similar to that of EPROM. In other words, the writing operation of EEPROM shown in FIG. 16 is performed by injecting into the floating gate 4 a hot carrier produced adjacent to the drain region 9 connected to the drain electrode 3. The threshold voltage of the storage transistor with respect to the control gate 6 is higher than that of another storage transistor which does not perform the writing operation, while such a writing operation is carried out. In the erasing operation, on the other hand, the control gate 6 is grounded, and the high voltage is applied to the source electrode 5, whereby the high electric field is produced between the floating gate 4 and the source region 9 connected to the source electrode 5. Then, while utilizing the tunneling phenomenon via the thin oxide film 7, the electron which has been stored in the floating gate 4 is drawn via the source region 9 to the source electrode. As a result, the stored information disappears. In other words, the threshold voltage of the storage transistor is lowered with respect to the control gate 6. During the reading operation, in order to prevent a weak writing operation from being undesirably effected to the above-described memory cell, that is, to prevent undesired carriers from being injected into the floating gate, the voltages applied to both the drain electrode 3 and control gate 6 are limited to a relatively lower value. A lower voltage of, for instance, on the order of 5 volts is applied to the control gate 6. A magnitude of a channel current flowing through the storage transistor is detected in accordance with such applied voltages so as to determine whether or not the information stored in the memory cell corresponds to “0” or “1.”
In general, during the electrical erasing operation, when the erasing operation is continued for a long time, the threshold voltage of the storage transistor will become different from that of the storage transistor under the thermal balance, namely it may become a negative value. To the contrary, in case of EPROM where the stored information is erased by way of ultraviolet radiation, the threshold voltage of the storage transistor which is varied in accordance with the erasing operation is substantially equal to the threshold voltage which is obtained when this memory device is manufactured. In other words, the threshold voltage of the storage transistor after the erasing operation may be controlled by the manufacturing conditions and the like of this memory device. However, as previously described, in the case that the stored information is electrically erased, the stored information disappears when the electron stored in the floating gate is drawn to the source electrode. As a consequence, if the erasing operation in connection with such an EEPROM as in FIG. 16 is continued for a relatively long time, a large quantity of electrons are drawn away from the floating gate into the source electrode via the source region as compared with a quantity of electrons which have been injected into the floating gate while the writing operation is carried out. Therefore, when the electrical disappearance or erasings of the stored information is continued for a relatively long time, the threshold voltage of the storage transistor attains a different value from the threshold voltage obtained when the memory device is manufactured. That is to say, when the erasing operation is performed, the threshold voltage of the storage transistor would no longer be equal to the threshold voltage determined by the manufacturing conditions thereof, in contrast to the EPROM.
The Applicants, in accordance with their investigative and research efforts, have measured the variations in the threshold voltage of the storage transistor caused by the electrical erasing operation. In FIG. 8, there is shown a relationship, based on such measured variations, between the threshold voltage of the storage transistor as varied by the length of the erasing operation. In the graphic representation shown in FIG. 8, the abscissa denotes the erase time, whereas the ordinate indicates the threshold voltage of the storage transistor. “Vo” indicates that the threshold voltage is substantially equal to zero, “+Vths” represents that the threshold voltage is equal to a positive voltage; and “−Vths” indicates that the threshold voltage is equal to a negative voltage. Also, “Vthv” represents a fluctuation in the threshold voltage after the erasing operation, which is caused by fluctuations and the like of the manufacturing conditions. From this figure, it should be understood that if the erasing operation is continued for a relatively long time, the threshold voltage with respect to an N-channel storage transistor, for example, is changed wherein it becomes a negative voltage. Similarly, it should be understood from this figure that different threshold voltage variations of the respective storage transistors may result by the erasing operation because of fluctuations in the manufacturing conditions. In addition, it should be understood from this figure that the fluctuations in the threshold voltage become large in accordance with the erasing time. That is to say, a difference in the threshold voltages of two storage transistors is enhanced or magnified in accordance with an increase in the erase time.
As previously described, when the threshold value of the storage transistor becomes negative, the readout operation becomes adversely influenced. This adverse influence will now be described with reference to FIG. 17. It is now assumed that the information stored is read from the memory cell 12 under the write condition. Reference numeral 17 shown in FIG. 17 indicates a sense amplifier. To bring the memory cell 12 into the selective condition, the selective voltage during the readout operation, for instance the power source voltage Vcc(5V) is applied to the word line 13 connected to the memory cell 12. During this time, the non-selection voltage (for example the ground voltage 0V) during the readout operation is supplied to the word lines 15 etc. in order to bring the other memory cells 14 etc. into the non-selective condition. If the memory cell 14, which is connected to the data line 16 as is the memory cell 12 from which the stored information is to be read out, is in the non-selective condition and has developed a negative threshold voltage, even if the voltage of the word line 15, namely the voltage of the control gate of the memory cell becomes zero, since the undesired current (non-selective leak current) flows through the data line 16 via the memory cell 14 which has been brought into the non-selective condition, a delay in a readout time may occur and thus an erroneous reading operation may be induced.
Similarly, there is an adverse influence with respect to a writing operation if the storage transistor within the memory cell has developed a negative threshold voltage. Normally, in the case where the writing operation is performed by utilizing hot carrier transfer, the high voltage (VPP) employed for the writing operation, which is externally applied, is applied via a switching MOSFET to the drain region of the storage transistor within the memory cell. The voltage drop in the above-described MOSFET is changed, depending upon the current flowing therethrough. As a consequence, under such a condition that the threshold voltage of the storage transistor becomes negative, the above-described voltage drop across the MOSFET becomes too large so that the voltage applied to the drain of the storage transistor within the memory cell is lowered by the above-described voltage drop. As a result, the time required for the writing operation may be increased.
Consequently, in the above-described EEPROM, a precise control must be implemented in order to control the value of the threshold value after the erasing operation.
In order to effect the electrical erasing operation of the stored information in a conventional EEPROM, for instance, as described on pages 152 to 153 in IEEE International Solid-State Circuit Conference in 1980, the EEPROM therein is constructed of storage transistors and selective transistors for blocking the non-selective leak current. Also, in this EEPROM, the program line is coupled to the control gate of the storage transistor thereof, whereas the selective line is coupled to the gate of the selective transistor. That is to say, both the storage transistor and selective transistor of each memory cell thereof are coupled to independent lines, respectively.
In FIG. 18, there is shown a sectional view of the memory cell of the electrical batch erasing type EEPROM which has been described on pages 76 to 77 in IEEE International Solid-State Circuit Conference in 1987. Although the operation of this memory cell is substantially the same as that of the memory cell shown in FIG. 16, the erasing operation of the stored information is different from that of the memory cell shown in FIG. 16. That is to say, the erasing operation of this EEPROM is carried out by utilizing the tunneling phenomenon effected between the floating gate and drain region. In this memory cell, though there is only one gate electrode to be connected to the word line, substantially two transistors are used to construct the memory cell. In other words, it can be assumed that the memory cell is arranged by the selective transistor and storage transistor in which both the gate electrode and control gate electrode are formed on a body. As previously described, since this memory cell essentially includes the selective transistor, the conventional problem of the nonselective leak current occurring during the readout time has been solved. However, since the writing operation is performed by the hot carrier required for a larger quantity of current, as compared with the writing operation effected by utilizing the tunneling phenomenon, the problem of the above-described adverse influence while the writing operation is executed is still present.
In the conventional EEPROM as described, for instance, on pages 152 to 153 in IEEE International Solid-State Circuit Conference in 1980, a single memory cell is constructed of a storage transistor and a selective transistor which are connected to respectively different word lines. However, in the memory cell of another type of EEPROM, such as of the electrically batch erasing type EEPROM as represented in FIGS. 16 and 18, it is constructed of a single storage transistor connected to a single word line. Such a specific arrangement as may be apparent in connection with the memory cells and the like shown in FIGS. 16 and 18 are herein represented by circuit diagrams. To this end, the representative circuit diagrams of the above-described memory cell are illustrated in FIGS. 19A and 19B. FIG. 19B shows a circuit diagram of the memory cell which has been announced at the IEEE International Solid-State Circuit Conference held in 1980. In the memory cell shown in FIG. 19B, symbols “W1” and “W2” denote different word lines, and symbol “D” represents a data line. Also, symbol “Qs” indicates a selective transistor whereas symbol “Qm” represents a storage transistor. FIG. 19A shows a circuit diagram of the memory cell shown in FIGS. 16 and 18. As is apparent from this circuit diagram, a single memory cell is so constructed that a control gate of a single storage transistor Qm is connected to a single word line, a drain thereof is connected to a single data line “D,” and a source thereof is connected to a single source line “S.” While the reading/writing operations are performed, to select a desired single memory cell from a plurality of memory cells of the type according to FIG. 19A, only a single word line and a single data line are required to be selected. This cell which is selected, of course, corresponds to the selected word line “W” and to the selected data line “D.” In other words, a single memory cell can be defined by one word line and one data line. It should be noted that in FIG. 19A, the source line “S” is commonly used as the source lines “S” of all of the remaining storage transistors formed on the chip. Alternatively, each source line “S” provided can be commonly used with respect to a predetermined number of memory cells constituting a single memory block.
Since the memory cell shown in FIG. 19A can be arranged by a single storage transistor, the area on the chip required for forming the memory cell can be reduced to a small area substantially equal to that of EPROM. However, in order to realize the electrically batch erasing operation of the stored information, as described above, it is absolutely necessary to be capable of controlling the threshold voltage of the storage transistor after the erasing operation.
To this end, according to prior efforts, the erasing operation is subdivided into a certain number of erasing operations. Then, a confirmation determination is made as to whether or not the erasing operation is sufficient. If the erasing operation performed is determined to be insufficient or inadequate, the erasing operation is again repeated. In accordance with the above-described IEEE, J. Solid-State Circuits vol. 23 (1988), pages 1157 to 1163, there is proposed an algorithm relating to a control of the threshold voltage after such an erasing operation. In accordance with this publication, this algorithm is executed by the microprocessor which is provided separately with the electrically batch erasing type EEPROM. Also, in order to maintain the lower limit voltage “Vcc min” of the operable power source during the normal read out operation, a description given therein requires that the verify voltage be generated in the chip of the EEPPOM while implementing the above-described algorithm (erasing verify operation).
In the above-described prior art, since such an algorithm is performed by the microprocessor, a cumbersome operation is required to perform the erasing operation of the stored information while the electrically batch erasing type EEPROM is actually packaged within the system. Furthermore, since a relatively long time is required for erasing the stored information, the microprocessor is necessarily being occupied for the erasing operation of the above-described EEPROM. This causes a serious problem in that the overall system employed must actually be stopped, i.e. be unnecessarily halted.
As the flash EEPROM, a typical memory device is disclosed, for example, in Japanese Patent Application Laid-Open Publication No. 62(1988)-276, 878.
The memory cell of the flash EEPROM will be herein called a FAST (Floating Gate Asymmetric Source and Drain Tunnel Oxide) type.
The FAST type memory cell has a construction of a floating gate type field-effect transistor similar to the FAMOS type of EPROM. One bit (one memory cell) can be constituted by one element, and excellent integration is therefore provided.
Writing is effected by injecting into a floating gate electrode a hot electron generated in the vicinity of a drain junction similar to FAMOS. A threshold voltage as viewed from a control gate electrode of the memory cell is increased by writing.
On the other hand, erasure is effected by grounding a control gate electrode, applying a positive high voltage to a source to thereby generate a high electric field between a floating gate electrode and the source, and drawing electrons accumulated on the floating gate electrode into the source utilizing a tunnel phenomenon through a thin gate oxide film. A threshold voltage as viewed from the control gate electrode is lowered by the erasure. Since the memory cell has not selective transistor, presence of negative threshold voltage (over-erasure state) is fatally defective.
Reading is effected by applying a low voltage of the order of 1 V to a drain, applying a voltage of the order of 5 V to a control gate electrode, and utilizing the fact that magnitude of a channel current floating at that time corresponds to “0” and “1” of information. The drain voltage is stepped down to prevent a parasitic weak writing operation.
Since in the aforementioned FAST type memory cell, writing and erasure are effected on the drain side and on the source side, respectively, it is desired that junction profiles are individually optimized so as to suit to respective operations. The above-described prior art has a source/drain asymmetric construction, in which in the drain junction, an electric field concentrated type profile for improving the writing efficiency is used whereas in the source junction, an electric field relaxation type profile capable of applying a high voltage is employed.
In a memory cell for effecting erasure drawing an electron from a floating gate electrode in a tunnel, how to minimize an electrostatic capacity coupling between a region (a source region in this instance) to which an erasure voltage is applied and a floating gate electrode is important in order to case the fineness of cell to be consistent with the lower voltage of erasure operation. In the FAST type memory cell, a superposed region of a floating gate electrode and a source for determining a capacity coupling is formed in a self-matching manner by diffusion of the source to reduce the value thereof.
Chip collective erasure type memories other than the above-described are as follows.
First, V. N. Kynett et al. disclose, in IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers, pp. 140-141, Fe., 1989, a 1 Mb flash EEPROM of the chip collective erasure type which uses a memory cell based on the principle similar to the aforementioned FAST type. A memory cell area is 15.2 μm2 (design rule; 1.0 μm), and a working voltage for writing and erasure is 12 V. The low voltage operation is realized in the fine cell. However, this apparatus requires to external power sources, Vcc (5 V) and Vpp (12 V) for writing. This is because of the fact that a consumption current during rewriting operation is so high that a step-up power source of on-chip cannot be utilized.
Furthermore, S. D'Arrigo et al. disclose, in IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers, pp. 132-133, February, 1989, a 256 kbit flash EEPROM of the chip collective erasure type. That is, (1) the tunnel phenomenon of electrons is utilized for writing as well as erasure, and (2) a region in which the gate oxide film used in the tunnel is thin is limited to a drain high concentration diffusion layer whereby a consumption current for rewriting operation may be reduced. A further feature of this memory is to apply a negative voltage to a control gate electrode in the erasure operation. Thereby, the voltage applied to the drain diffusion layer is stepped down to 5 V or so to increase an allowance with respect to junction pressure. However, in this apparatus, the tunnel region is not self-matched. Further, a selective transistor called a pass gate is contained in the cell, and therefore, this apparatus is inferior to the FAST type in terms of the fineness of cell and the low voltage operation.